#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <asm/mach/map.h>
#include <mach/pmu.h>
#include <mach/clock.h>
#include "chip.h"

/*
 * external oscillator
 * fixed to 24M
 */
static struct fh_clk osc_clk = {
	.name               = "osc_clk",
	.frequency          = OSC_FREQUENCY,
	.flag               = CLOCK_FIXED,
};

static struct fh_clk cis_pix_clk = {
	.name               = "cis_pix_clk",
	.frequency          = 75000000,
	.flag               = CLOCK_FIXED,
};

static struct fh_clk acodec_pll_clk = {
	.name               = "acodec_pll_clk",
	.frequency          = 98304000,
	.flag               = CLOCK_FIXED,
};

/*
 * phase-locked-loop device,
 * generates a higher frequency clock
 * from the external oscillator reference
 */
static struct fh_clk pll0_clk = {
	.name               = "pll0_clk",
	.flag               = CLOCK_PLL,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL0,
};

static struct fh_clk pll1_clk = {
	.name               = "pll1_clk",
	.flag               = CLOCK_PLL,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL1,
};

/*
 * CPU
 */
static struct fh_clk arm_clk = {
	.name               = "arm_clk",
	.flag               = CLOCK_NOGATE|CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &pll1_clk, &osc_clk, &pll0_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf,
	.sel_reg_offset     = REG_PMU_SYS_CTRL,
	.sel_reg_mask       = 0x3,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x80000000,
};

static struct fh_clk arc_clk = {
	.name               = "arc_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &pll0_clk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_SYS_CTRL,
	.sel_reg_mask       = 0x1,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x4,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf0,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x400000,
};

/*
 * BUS
 */
static struct fh_clk ahb_clk = {
	.name               = "ahb_clk",
	.flag               = CLOCK_NOGATE | CLOCK_NORESET|CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &pll0_clk},
	.prediv             = 2,
	.sel_reg_offset     = REG_PMU_SYS_CTRL,
	.sel_reg_mask       = 0x1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf0,
};


/*
 * ip
 */
static struct fh_clk pll1_clk_div_2 = {
	.name				= "pll1_clk_div_2",
	.prediv				= 2,
	.flag				= CLOCK_NODIV | CLOCK_NOGATE,
	.parent				= {&pll1_clk},
};

static struct fh_clk ddr_clk = {
	.name               = "ddr_clk",
	.flag               = CLOCK_NODIV | CLOCK_MULTI_PARENT,
	.parent             = {&pll0_clk, &pll1_clk_div_2},
	.prediv             = 1,
	.sel_reg_offset		= REG_PMU_CLK_SEL,
	.sel_reg_mask		= 0x1,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x40,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x10000,
};

static struct fh_clk isp_aclk = {
	.name               = "isp_aclk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&pll0_clk, &pll1_clk},
	.prediv             = 1,
	.sel_reg_offset		= REG_PMU_CLK_SEL,
	.sel_reg_mask		= 0x10,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0x1f00,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x1,
	.rst_reg_offset		= REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask		= 0x400000,

};

static struct fh_clk isp_hclk = {
	.name               = "isp_hclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x2,
};


static struct fh_clk bgm_clk = {
	.name               = "bgm_clk",
	.flag				= CLOCK_MULTI_PARENT,
	.parent				= {&pll0_clk, &pll1_clk},
	.prediv				= 1,
	.sel_reg_offset		= REG_PMU_CLK_SEL,
	.sel_reg_mask		= 0x10,
	.div_reg_offset		= REG_PMU_CLK_DIV4,
	.div_reg_mask		= 0x1f00,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x100000,
	.rst_reg_offset		= REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask		= 0x2000000,

};

static struct fh_clk bgm_hclk = {
	.name               = "bgm_hclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE2,
	.en_reg_mask        = 0x200000,
};

static struct fh_clk jpeg_clk = {
	.name               = "jpeg_clk",
	.flag				= CLOCK_MULTI_PARENT,
	.parent				= {&pll0_clk, &pll1_clk},
	.prediv				= 1,
	.sel_reg_offset		= REG_PMU_CLK_SEL,
	.sel_reg_mask		= 0x10,
	.div_reg_offset		= REG_PMU_CLK_DIV4,
	.div_reg_mask		= 0x1f00,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x40000,
	.rst_reg_offset		= REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask		= 0x1000000,

};

static struct fh_clk jpeg_hclk = {
	.name               = "jpeg_hclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE2,
	.en_reg_mask        = 0x80000,
};


static struct fh_clk pae_clk = {
	.name               = "pae_clk",
	.parent             = {&pll0_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0x7000000,
	.en_reg_offset      = REG_PMU_CLK_GATE2,
	.en_reg_mask        = 0x400000,
	.rst_reg_offset		= REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask		= 0x800000,

};

static struct fh_clk cis_clk_div = {
	.name               = "cis_clk_div",
	.flag               = CLOCK_NOGATE | CLOCK_CIS,
	.parent             = {&pll0_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0x1f000000,
};

static struct fh_clk cis_clk_out = {
	.name               = "cis_clk_out",
	.flag               =  CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &cis_clk_div},
	.prediv             = 1,
	.sel_reg_offset	    = REG_PMU_CLK_SEL,
	.sel_reg_mask       = 0x8,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x800000,
};

static struct fh_clk cis_pix_clk_rt = {
	.name               = "cis_pix_clk_rt",
	.flag               = CLOCK_FIXED,
	.frequency          = 75000000,
};

static struct fh_clk mipi_pix_clk = {
	.name               = "mipi_pix_clk",
	.flag               = CLOCK_NORESET | CLOCK_NOGATE | CLOCK_MULTI_PARENT,
	.parent             = {&pll0_clk, &pll1_clk},
	.prediv             = 1,
	.sel_reg_offset		= REG_PMU_CLK_SEL,
	.sel_reg_mask		= 0x20,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0x1f0000,
};

static struct fh_clk pix_clk = {
	.name               = "pix_clk",
	.flag               = CLOCK_NORESET | CLOCK_NODIV | CLOCK_MULTI_PARENT,
	.parent				= {&cis_pix_clk, &cis_pix_clk_rt, &mipi_pix_clk, &mipi_pix_clk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL,
	.sel_reg_mask       = 0x60,
	.en_reg_offset      = REG_PMU_CLK_GATE2,
	.en_reg_mask        = 0x20000,
};

static struct fh_clk dw_100m_clk = {
	.name               = "dw_100m_clk",
	.flag               = CLOCK_NORESET | CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&pll1_clk},
	.prediv             = 6,
};

static struct fh_clk dw_50m_clk = {
	.name               = "dw_50m_clk",
	.flag               = CLOCK_NORESET | CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&dw_100m_clk},
	.prediv             = 2,
};


static struct fh_clk sdc0_clk = {
	.name               = "sdc0_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 2,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf0000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x200,
	.rst_reg_offset     = REG_PMU_SWRST_AHB_CTRL,
	.rst_reg_mask       = 0x1000,
};

static struct fh_clk sdc1_clk = {
	.name               = "sdc1_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 2,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf00000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x400,
	.rst_reg_offset     = REG_PMU_SWRST_AHB_CTRL,
	.rst_reg_mask       = 0x800,
};

static struct fh_clk spi0_clk = {
	.name               = "spi0_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf00,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x80,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x2000,
};

static struct fh_clk spi1_clk = {
	.name               = "spi1_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x100,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x4000,
};

static struct fh_clk i2c0_clk = {
	.name               = "i2c0_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0x3f,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x1000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x200,
};

static struct fh_clk i2c1_clk = {
	.name               = "i2c1_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0x3f00,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x8000000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x100,
};

static struct fh_clk i2c2_clk = {
	.name               = "i2c2_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0x3f0000,
	.en_reg_offset      = REG_PMU_CLK_GATE1,
	.en_reg_mask        = 0x200,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x80,
};

static struct fh_clk uart0_clk = {
	.name               = "uart0_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0x1f,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x2000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x1000,
	.def_rate           = 16666666,
};

static struct fh_clk uart1_clk = {
	.name               = "uart1_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0x1f00,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x4000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x800,
	.def_rate           = 16666666,
};

static struct fh_clk uart2_clk = {
	.name               = "uart2_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0x1f0000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x8000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x400,
	.def_rate           = 16666666,
};

static struct fh_clk pwm_clk = {
	.name               = "pwm_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0xff000000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x10000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x10,
	.def_rate	    = 25000000,
};

static struct fh_clk efuse_clk = {
	.name               = "efuse_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf0000000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x200000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x20,
};


static struct fh_clk pts_clk = {
	.name               = "pts_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV3,
	.div_reg_mask       = 0x1ff0000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x80000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x1,
};

static struct fh_clk tmr0_clk = {
	.name               = "tmr0_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV3,
	.div_reg_mask       = 0xff,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x20000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x2,
};

static struct fh_clk sadc_clk = {
	.name               = "sadc_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0x7f,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x4000000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x8,
};

static struct fh_clk gpio0_dbclk = {
	.name               = "gpio0_dbclk",
	.parent             = {&dw_100m_clk},
	.prediv             = 100,
	.div_reg_offset     = REG_PMU_CLK_DIV5,
	.div_reg_mask       = 0x7fff,
	.en_reg_offset      = REG_PMU_CLK_GATE1,
	.en_reg_mask        = 0x800,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x8000,
};

static struct fh_clk gpio1_dbclk = {
	.name               = "gpio1_dbclk",
	.parent             = {&dw_100m_clk},
	.prediv             = 100,
	.div_reg_offset     = REG_PMU_CLK_DIV5,
	.div_reg_mask       = 0x7fff0000,
	.en_reg_offset      = REG_PMU_CLK_GATE1,
	.en_reg_mask        = 0x2000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x200000,
};

static struct fh_clk eth_clk = {
	.name               = "eth_clk",
	.parent             = {&dw_100m_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xf000000,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x2000000,
	.rst_reg_offset     = REG_PMU_SWRST_AHB_CTRL,
	.rst_reg_mask       = 0x400,
};

static struct fh_clk eth_rmii_clk = {
	.name               = "eth_rmii_clk",
	.flag				= CLOCK_NORESET | CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE0,
	.en_reg_mask        = 0x10000000,
};



static struct fh_clk wdt_clk = {
	.name               = "wdt_clk",
	.parent             = {&ahb_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV3,
	.div_reg_mask       = 0xff00,
	.en_reg_offset      = REG_PMU_CLK_GATE1,
	.en_reg_mask        = 0x4,
	.rst_reg_offset     = REG_PMU_SWRST_APB_CTRL,
	.rst_reg_mask       = 0x80000,
};
	static struct fh_clk usb_clk = {
	.name				= "usb_clk",
	.flag				= CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent				= {&osc_clk, &dw_50m_clk},
	.prediv				= 1,
	.sel_reg_offset		= REG_PMU_CLK_SEL,
	.sel_reg_mask		= 0x8000,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x2000,
	};

static struct fh_clk ac_clk = {
	.name               = "ac_clk",
	.parent             = {&osc_clk, &acodec_pll_clk},
	.flag				= CLOCK_MULTI_PARENT,
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_I2SCLK_CTRL,
	.div_reg_mask       = 0x3f0,
	.en_reg_offset      = REG_PMU_I2SCLK_CTRL,
	.en_reg_mask        = 0x100000,
	.sel_reg_offset     = REG_PMU_I2SCLK_CTRL,
	.sel_reg_mask       = 0x1,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x40,
};

static struct fh_clk i2s_clk = {
	.name               = "i2s_clk",
	.parent             = {&ac_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_I2SCLK_CTRL,
	.div_reg_mask       = 0x3f000,
	.en_reg_offset      = REG_PMU_I2SCLK_CTRL,
	.en_reg_mask        = 0x1000000,
	.rst_reg_offset     = REG_PMU_SWRST_MAIN_CTRL,
	.rst_reg_mask       = 0x100000,
};

#if 1

static struct fh_clk pll0_cis_clk = {
	.name               = "pll0_cis_clk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x10,
};

static struct fh_clk emc_hclk_gate = {
	.name               = "emc_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x1,
};

static struct fh_clk rtc_pclk_gate = {
	.name               = "rtc_pclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x2,
};

static struct fh_clk aes_hclk_gate = {
	.name               = "aes_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x20,
};

static struct fh_clk dmac0_hclk_gate = {
	.name               = "dmac0_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x40,
};

static struct fh_clk dmac1_hclk_gate = {
	.name               = "dmac1_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x80,
};

static struct fh_clk intc_hclk_gate = {
	.name               = "intc_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x100,
};

static struct fh_clk ddrc_hclk_gate = {
	.name               = "ddrc_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x8000,
};

static struct fh_clk mipi_dphy_clk = {
	.name               = "mipi_dphy_clk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x400,
};

static struct fh_clk mipi_wrap_pclk = {
	.name               = "mipi_wrap_pclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x800,
};

static struct fh_clk mipic_pclk = {
	.name               = "mipic_pclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x1000,
};



static struct fh_clk usb_hclk = {
	.name               = "usb_hclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x4000,
};

static struct fh_clk acodec_mclk = {
	.name               = "acodec_mclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x8000,
};
static struct fh_clk acodec_pclk = {
	.name               = "acodec_pclk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x10000,
};

static struct fh_clk pae_hclk_gate = {
	.name               = "pae_hclk_gate",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x800000,
};
static struct fh_clk multi_pae_clk = {
	.name               = "multi_pae_clk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x200,
};

static struct fh_clk pae_adpt_clk = {
	.name               = "pae_adpt_clk",
	.flag               = CLOCK_NODIV | CLOCK_NORESET,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x1000000,
};

static struct fh_clk sdc0_clk_sample = {
	.name               = "sdc0_clk_sample",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL,
	.sel_reg_mask       = 0x600,
};

static struct fh_clk sdc0_clk_drv = {
	.name               = "sdc0_clk_drv",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL,
	.sel_reg_mask       = 0x180,
};

static struct fh_clk sdc1_clk_sample = {
	.name               = "sdc1_clk_sample",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL,
	.sel_reg_mask       = 0x6000,
};

static struct fh_clk sdc1_clk_drv = {
	.name               = "sdc1_clk_drv",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL,
	.sel_reg_mask       = 0x1800,
};



#endif


struct fh_clk *fh_clks[] = {
	 &osc_clk,
	 &cis_pix_clk,
	 &acodec_pll_clk,
	 &pll0_clk,
	 &pll1_clk,
	 &arm_clk,
	 &arc_clk,
	 &ahb_clk,
	 &pll1_clk_div_2,
	 &ddr_clk,
	 &isp_aclk,
	 &isp_hclk,
	 &pae_clk,
	 &bgm_clk,
	 &bgm_hclk,
	&jpeg_clk,
	&jpeg_hclk,
	&cis_clk_div,
	&cis_clk_out,
	&cis_pix_clk_rt,
	&mipi_pix_clk,
	&pix_clk,
	&dw_100m_clk,
	&dw_50m_clk,
	&pts_clk,
	&spi0_clk,
	&spi1_clk,
	&sdc0_clk,
	&sdc1_clk,
	&uart0_clk,
	&uart1_clk,
	&uart2_clk,
	&i2c0_clk,
	&i2c1_clk,
	&i2c2_clk,
	&pwm_clk,
	&wdt_clk,
	&usb_clk,
	&tmr0_clk,
	&gpio0_dbclk,
	&gpio1_dbclk,
	&ac_clk,
	&i2s_clk,
	&sadc_clk,
	&eth_clk,
	&eth_rmii_clk,
	&efuse_clk,
	&pae_hclk_gate,
	&multi_pae_clk,
	&pae_adpt_clk,
	&pll0_cis_clk,
	&emc_hclk_gate,
	&rtc_pclk_gate,
	&aes_hclk_gate,
	&dmac0_hclk_gate,
	&dmac1_hclk_gate,
	&intc_hclk_gate,
	&ddrc_hclk_gate,
	&mipi_dphy_clk,
	&mipi_wrap_pclk,
	&mipic_pclk,
	&usb_hclk,
	&acodec_mclk,
	&acodec_pclk,
	&sdc0_clk_sample,
	&sdc0_clk_drv,
	&sdc1_clk_sample,
	&sdc1_clk_drv,
	NULL,
};
EXPORT_SYMBOL(fh_clks);
